Threshold voltage (Vt) is an important parameter to be able to control in metal oxide semiconductor field effect transistor (MOSFET) devices. In bulk MOSFET designs wherein the channel is formed in a bulk semiconductor, the Vt is commonly adjusted through doping. It is often desirable to have multiple Vt's in a MOSFET design wherein the Vt varies from one device to another.
Setting multiple Vt's in a fully depleted technology presents many challenges, as doping to adjust Vt is no longer an option. It has been found that the Vt of planar p-channel FETs can be adjusted through oxidation of the high-κ gate dielectric. See for example, Cartier et al., “pFET Vt control with HfO2/TiN/poly-Si gate stack using a lateral oxygenation process,” 2009 Symposium on VLSI Technology, pgs. 42-43 (June 2009) (hereinafter “Cartier”) and U.S. Patent Application Publication Number 2009/0289306 A1 by Watanabe et al., entitled “Lateral Oxidation with High-k Dielectric Liner” (hereinafter “U.S. Patent Application Publication Number 2009/0289306 A1”).
There however exists a need for controlling Vt in non-planar device configurations.